Designing an integrated circuit is complicated because each design involves specifying millions of transistors and wires. The way IC designers make such complicated system designs more tractable is to use hierarchy, in which wires and transistors are grouped together into functional cells, and those cells are then grouped into functional blocks. The numerical problem of extracting functional cell descriptions from transistors and wires, or extracting block descriptions from cells, is often referred to as model-order reduction because the problem can usually be recast as one of generating

low-order dynamical systems which preserve the input-output behavior of much higher-order dynamical systems. In this talk we will survey the recent developments in numerical model-order reduction for linear problems, by trying to connect Krylov-subspace based methods, Pade approximates, and truncated balanced realizations. We will then describe some of the challenges in extending these approaches to nonlinear problems.