The Integrated Circuits (IC) industry has been able to double the number of the transistors, the switching elements, on a computer chip every 18 months. This is done by reducing the size of the transistors. Currently, transistor sizes range between14 to 7 nm. This growth in technology has, on one hand, forced the engineers to solve very large-scale problems, while on the other hand, they have to deal with unavoidable uncertainties that exist because of the small sizes of the transistors. In this talk, we will discuss case studies in IC physical design where large scale problems or problems that include uncertainties are solved using convex optimisation methods, and how convex optimisation methods can be integrated with heuristics to find reasonably good solutions in low runtime.